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? semiconductor components industries, llc, 2014 april, 2014 ? rev. 10 1 publication order number: ncp6914/d ncp6914 5 channel pmic: 1 dcdc converter and 4 ldos the ncp6914 integrated circuits are part of the on semiconductor mini power management ic family (pmic). they are optimized to supply battery powered portable application sub?systems such as camera function and microprocessors. these devices integrate 1 high efficiency 800 ma step?down dc to dc converter with dvs (dynamic voltage scaling) and four low?dropout (ldo) voltage regulators in a wlcsp20 1.77 x 2.06 mm package. features ? 1 dcdc converter (3 mhz, 1 h/10 f, 800 ma) ? peak efficiency 95% ? programmable output voltage from 0.6 v to 3.3 v by 12.5 mv steps ? 4 low noise ? low dropout regulators (300 ma) ? programmable output voltage from 1.0 v to 3.3 v by 50 mv steps ? 50 v rms typical low output noise ? control ? 400 khz / 3.4 mhz i 2 c compatible ? hardware enable pin ? power good and interrupt output pin ? external synchronization ? customizable power up sequencer ? extended input voltage range 2.3 v to 5.5 v ? optimized power efficiency ? 72 a very low quiescent current at no load ? less than 1 a off mode current ? small footprint: package 1.77 x 2.06 mm wlcsp ? these are pb?free devices typical applications ? cellular phones ? digital cameras ? personal digital assistant and portable media player ? gps systems power state indicator processor interrupt processor i c battery or system supply processor or system supply system supply dcdc1 out system or dcdc supply system or dcdc supply ldo3 out ldo4 out 4.7 uf 10 uf 1uh 2.2uf 2.2uf 1.0uf ldo2 out 2.2uf ldo1 out 2.2uf system or dcdc supply 100 nf ncp6914 core ldo 3 300 ma ldo 4 300 ma ldo 1 300 ma ldo 2 300 ma avin agnd vin3 vout3 vin4 vout4 fb1 pvin1 sw1 pgnd1 vout1 vin12 vout2 interrupt enabling supply monitoring power up sequencer thermal protection sda scl sync pg hwen intb vbg rev 1. 00 dcdc 1 800 ma b3 b4 a4 c1 d3 c2 d2 c3 b2 b1 a1 a3 a2 e4 d4 c4 e1 e3 e2 d1 clocking figure 1. application schematic i 2 c wlcsp20 case 567cv marking diagram* http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 35 of this data sheet. ordering information x = a for ncp6914aa = b for ncp6914ab = d for ncp6914ad a = assembly location wl = wafer lot y = year ww = work week = pb?free package (pb?free indicator, ?g? or microdot ? ?, may or may not be present.) a b c d e 123 4 vin4 vout4 hwen pvin1 pgnd1 vin3 pg sda scl sw1 vout3 avin sync intb fb1 vbg agnd vout1 vin12 vout2 (top view) 20?pin 1.77 x 2.06 mm wlcsp, 0.40 mm pitch 6914ax awlyww
ncp6914 http://onsemi.com 2 figure 2. functional block diagram dcdc 800 ma step?down converter pvin1 sw1 fb1 pgnd1 vldo1 300 ma ldo vldo2 300 ma ldo vin12 vout1 vout2 vldo4 300 ma ldo vout4 vin4 agnd thermal shutdown serial interface scl sda control hwen intb uvlo vref osc pg vbg avin vldo3 300 ma ldo vout3 vin3 sync
ncp6914 http://onsemi.com 3 a b c d e 123 4 vin4 vout4 hwen pvin1 pgnd1 vin3 pg sda scl sw1 vout3 avin sync intb fb1 vbg agnd vout1 vin12 vout2 figure 3. pin out (top view) table 1. pinout description pin name type description power b3 avin analog input analog supply. this pin is the device analog and digital supply. a 1.0 f ceramic capacitor or larger must bypass this input to ground. this capacitor should be placed as close as possible to this pin. a4 vbg analog output reference voltage. a 0.1 f ceramic capacitor must bypass this pin to the system ground. b4 agnd analog ground analog ground. analog and digital modules ground. must be connected to the system ground. control and serial interface c1 hwen digital input hardware enable. active high will enable the part. there is an internal pull down resistor on this pin. c3 sync digital input external synchronization input. d2 scl digital input i 2 c interface clock. c2 sda digital input/output i 2 c interface data. b2 pg digital output power good. open drain output . d3 intb digital output interrupt. open drain output . dcdc converter d1 pvin1 power input dcdc power supply. this pin must be decoupled to ground by a 4.7 f ceramic capacitor. this capacitor should be placed as close as possible to this pin. e2 sw1 power output dcdc switch power. this pin connects the power transistors to one end of the inductor. typical application uses 1.0 h inductor; refer to application section for more information. e3 fb1 analog input dcdc feedback voltage. this pin is the input to the error amplifier and must be connected to the output capacitor. e1 pgnd1 power ground dcdc power ground. this pin is the power ground and carries the high switching current. a high quality ground must be provided to prevent noise spikes. a local ground plane is recommended to avoid high?density current flow in a limited pcb track. ldo regulators d4 vin12 power input ldo 1&2 power supply. c4 vout1 power output ldo 1 output power. this pin requires a 2.2 f decoupling capacitor. e4 vout2 power output ldo 2 output power. this pin requires a 2.2 f decoupling capacitor. a2 vin3 power input ldo 3 power supply. a3 vout3 power output ldo 3 output power. this pin requires a 2.2 f decoupling capacitor. a1 vin4 power input ldo 4 power supply. b1 vout4 power output ldo 4 output power. this pin requires a 2.2 f decoupling capacitor.
ncp6914 http://onsemi.com 4 table 2. maximum ratings (note 1) symbol rating value unit v a analog and power pins: avin, pvin1, sw1, vin12, vin3, vin4, vout1, vout2, vout3, vout4, pg, intb, fb1, vbg ?0.3 to + 6.0 v v dg i dg digital pins: scl, sda, hwen, sync: input voltage input current ?0.3 to v a +0.3 6.0 10 v ma esd hbm human body model (hbm) esd rating (note 2) 2000 v esd mm machine model (mm) esd rating (note 2) 200 v i lu latch up current: (note 3) all digial pins all other pins 10 100 ma t stg storage temperature range ?65 to + 150 c t jmax maximum junction temperature ?40 to +150 c msl moisture sensitivity (note 4) level 1 stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. all voltages are related to agnd. 2. esd rated the following: human body model (hbm) 2.0 kv per jedec standard: jesd22?a114. machine model (mm) 200 v per jedec standard: jesd22?a115. 3. latch up current per jedec standard: jesd78 class ii. 4. moisture sensitivity level (msl): 1 per ipc/jedec standard: j?std?020a. table 3. recommended operating conditions symbol parameter conditions min typ max unit av in, pv in power supply 2.3 ? 5.5 v ldo vin ldo input voltage range 1.7 ? 5.5 v t a ambient temperature range ?40 25 +85 c t j junction temperature range (note 6) ?40 25 +125 c r ja thermal resistance junction?to?ambient (note 7) csp?20 on demo?board ? 60 ? c/w p d power dissipation rating (note 8) t a 85 c ? 660 ? mw p d power dissipation rating (note 8) t a = 40 c ? 1400 ? mw l inductor for dcdc converter (note 5) 0.47 1 2.2 h co output capacitor for dcdc converter (note 5) ? 10 ? f output capacitors for ldo (note 5) 1.20 2.2 ? f c in input capacitor for dcdc converter (note 5) ? 4.7 ? f functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. 5. refer to the application information section of this data sheet for more details. 6. the thermal shutdown set to 150 c (typical) avoids potential irreversible damage on the device due to power dissipation. 7. the r ja is dependent of the pcb heat dissipation. board used to drive this data was a ncp6914evb board. it is a multilayer board with 1?once internal power and ground planes and 2?once copper traces on top and bottom of the board. 8. the maximum power dissipation (p d ) is dependent by input voltage, maximum output current and external components selected. r ja 125 t a p d
ncp6914 http://onsemi.com 5 table 4. electrical characteristics min & max limits apply for t j up to +125 c unless otherwise specified. av in = pv in1 = v in12 = v in3 = v in4 = 3.6 v (unless otherwise noted). dcdc output voltage = 1.2 v, ldo1&2 = 1.8 v, ldo3&4 = 2.8 v, typical values are referenced to t j = + 25 c and default configuration (note 10) symbol parameter conditions min typ max unit supply current: pins avin ? pvin1 i q operating quiescent current dcdc on ? no load ? no switching ldos off t a = up to +85 c ? 32 70 a dcdc on ? no load ? no switching ldos on ? no load t a = up to +85 c ? 72 190 dcdc off all ldos on ? no load t a = up to +85 c ? 55 100 a i sleep product sleep mode current hwen on dcdc and all ldos off t a = up to +85 c ? 7 15 a i off product off current hwen off i 2 c interface disabled v in = 2.3 v to 5.5 v t a = up to +85 c ? 0.1 2.0 a dcdc converter pv in input voltage range 2.3 ? 5.5 v i outmax maximum output current 0.8 ? ? a vout output voltage dc error io = 300 ma, pwm mode t a = up to +85 c ?1 0 1 % f sw switching frequency 2.7 ? 3.3 mhz r onhs p?channel mosfet on res- istance from pvin1 to sw1, t a = up to +85 c guarantee by design and characterization, production tested at vin = 3.6 v ? 230 ? m r onls n?channel mosfet on res- istance from sw1 to pgnd1, t a up to 85 c guarantee by design and characterization, production tested at vin=3.6 v ? 200 ? m i pk peak inductor current open loop 2.3 v pv in 5.5 v 1.0 1.3 1.6 a load regulation i out from 300 ma to i outmax ? 5 ? mv/a line regulation i out = 300 ma 2.3 v v in 5.5 v ? 0 ? %/v d maximum duty cycle ? 100 ? % t start soft?start time time from i 2 c command ack to 90% of output voltage ? ? 1 ms r disdcdc dcdc active output discharge ? 7 ? ldo1 and ldo2 v in12 ldo1 and ldo2 input voltage range 300 ma load v out 1.3 v, i out = 300 ma 1.7 ? 5.5 v v out > 1.3 v, i out = 300 ma v out + v drop ? 5.5 i outmax1,2 maximum output current 300 ? ? ma i sc1,2 short circuit protection 360 ? 700 ma 9. devices that use non?standard supply voltages which do not conform to the intent i 2 c bus system levels must relate their input levels to the v dd voltage to which the pull?up resistors r p are connected. 10. refer to the application information section of this data sheet for more details. 11. guaranteed by design and characterized.
ncp6914 http://onsemi.com 6 table 4. electrical characteristics min & max limits apply for t j up to +125 c unless otherwise specified. av in = pv in1 = v in12 = v in3 = v in4 = 3.6 v (unless otherwise noted). dcdc output voltage = 1.2 v, ldo1&2 = 1.8 v, ldo3&4 = 2.8 v, typical values are referenced to t j = + 25 c and default configuration (note 10) symbol unit max typ min conditions parameter ldo1 and ldo2 v out1,2 output voltage accuracy dc i out = 300 ma ?2 v nom +2 % load regulation i out = 0 ma to 300 ma ? 0.4 ? % line regulation v in = max (1.7 v, v out + v drop ) to 5.5 v i out = 300 ma ? 0.3 ? % v drop dropout voltage i out = 300 ma, v out = v nom ? 2% ? 140 400 mv psrr ripple rejection f = 1 khz, i out = 150 ma ? ?75 ? db f = 10 khz, i out = 150 ma ? ?60 ? noise 10 hz 100 khz, i out = 150 ma ? 50 ? v r disldo1,2 ldo active output discharge ? 25 ? ldo3 and ldo4 v in3 , v in4 ldo3 and ldo4 input voltage v out 1.5 v, i out = 300 ma 1.7 ? 5.5 v v out > 1.5 v, i out = 300 ma v out + v drop ? 5.5 i outmax3,4 maximum output current 300 ? ? ma i sc3,4 short circuit protection 360 ? 700 ma v out output voltage accuracy i out = 300 ma ?2 v nom +2 % load regulation i out = 0 ma to 300 ma ? 0.4 ? % line regulation v drop to 5.5 v i out = 300 ma ? 0.3 ? % v drop dropout voltage i out = 300 ma v out = v nom ? 2% ? 90 200 mv psrr ripple rejection f = 1 khz, i out = 150 ma ? ?75 ? db f = 10 khz, i out = 150 ma ? ?60 ? noise 10 hz 100 khz, i out = 150 ma ? 50 ? v r disldo3,4 ldo active output discharge ? 25 ? sync clkin pk?p k input clock signal amplitude square waveform, 3 mhz/, 50% dc 800 ? ? mv sine waveform, 3 mhz 800 ? ? clkin dc input clock signal duty cycle square waveform, 3 mhz 30 ? ? % clkin v input clock voltage level sine waveform, 3 mhz, (note 11) ?0.3 ? 5.0 v f clockint external synchronization clock range after divider ratio (note 11) 2.55 ? 3.45 mhz f range external synchronization oper- ating frequency range square signal 50% duty cycle input signal on sync pin syncratio = 00001b to 01100b syncauto = 1 (note 11) 2.55 ? 100 mhz clkin pk?pk input clock signal amplitude square waveform, 3 mhz/, 50% dc 800 ? ? mv 9. devices that use non?standard supply voltages which do not conform to the intent i 2 c bus system levels must relate their input levels to the v dd voltage to which the pull?up resistors r p are connected. 10. refer to the application information section of this data sheet for more details. 11. guaranteed by design and characterized.
ncp6914 http://onsemi.com 7 table 4. electrical characteristics min & max limits apply for t j up to +125 c unless otherwise specified. av in = pv in1 = v in12 = v in3 = v in4 = 3.6 v (unless otherwise noted). dcdc output voltage = 1.2 v, ldo1&2 = 1.8 v, ldo3&4 = 2.8 v, typical values are referenced to t j = + 25 c and default configuration (note 10) symbol unit max typ min conditions parameter hwen v ih positive going input high voltage threshold 1.1 ? ? v v il negative going input low voltage threshold ? ? 0.4 v t hwen hardware enable filter hwen rising and falling (note 11) 4 ? 9 s i hwen hardware enable pull?down (input bias current) ? 0.1 1 a pg v pgl power good low threshold v out falls down to cross the threshold (percentage of fb voltage) 86 90 of v nom 94 % v pghys power good hysteresis v out rises up to cross the threshold (percentage of power good low threshold (v pgl ) voltage) 0 3 5 % t rt power good reaction time for dcdc falling (note 11) rising (note 11) ? 4 5 ? ? 9 s v pgl power good low output voltage i pg = 5 ma ? ? 0.2 v pg lk power good leakage current 3.6 v at pg pin when power good valid ? ? 100 na v pgh power good high output voltage open drain ? ? 5.5 v intb v intbl intb low output voltage i int = 5 ma 0 ? 0.2 v v intbh intb high output voltage open drain ? ? 5.5 v intb lk intb leakage current 3.6 v at intb pin when intb valid ? ? 100 na i 2 c v i2cint high level at scl/sda line ? ? 5.0 v v i2cil scl, sda low input voltage scl, sda pin (notes 9 and 11) ? ? 0.5 v v i2cih scl, sda high input voltage scl, sda pin (notes 9 and 11) 0.8 x v i2cint ? ? v v i2col scl, sda low output voltage i sink = 3 ma (note 11) ? ? 0.4 v f scl i 2 c clock frequency ? ? 3.4 mhz total device v uvlo under voltage lockout v in falling ? ? 2.3 v v uvloh under voltage lockout hysteresis v in rising 60 ? 200 mv t sd thermal shut down protection 150 c t warning warning rising edge 135 c t sdh thermal shut down hysteresis 35 c 9. devices that use non?standard supply voltages which do not conform to the intent i 2 c bus system levels must relate their input levels to the v dd voltage to which the pull?up resistors r p are connected. 10. refer to the application information section of this data sheet for more details. 11. guaranteed by design and characterized. product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
ncp6914 http://onsemi.com 8 typical operating characteristics figure 4. efficiency vs. i out (auto pfm / pwm mode) l = 1.0 h (lqh44pn1r0nj0) c out = 10 f (0603 size) v out = 1.2v figure 5. efficiency vs. i out (auto pfm / pwm mode) l = 1.0 h (lqh44pn1r0nj0) c out = 10 f (0603 size) v out = 1.8v figure 6. efficiency vs. i out (auto pfm / pwm mode) l = 1.0 h (lqh44pn1r0nj0) c out = 10 f (0603 size) v out = 2.8 v figure 7. efficiency vs. i out (auto pfm / pwm mod e) l = 1.0 h (lqh44pn1r0nj0) c out = 10 f (0603 size) v out = 3.3 v
ncp6914 http://onsemi.com 9 typical operating characteristics figure 8. ripple voltage in pwm mode (v in = 3.6 v ? v out 1.2 v) figure 9. ripple voltage in pfm mode (v in = 3.6 v ? v out 1.2 v) figure 10. i 2 c shutdown sequence with active discharge enabled figure 11. hwen shutdown sequence with active discharge disabled
ncp6914 http://onsemi.com 10 typical operating characteristics figure 12. load transient response of dcdc converter (pwm mode, v in = 3.6 v ? v out = 1.2 v) figure 13. dcdc soft?start (inrush current, v in = 3.6 v ? v out = 1.2 v) figure 14. ldo1 load transient response (v in = 3.6 v ? v out = 1.8 v) figure 15. ldo3 load transient response
ncp6914 http://onsemi.com 11 figure 16. ldo1 psrr figure 17. ldo1 outputs noise figure 18. ldo4 psrr figure 19. ldo4 output noise
ncp6914 http://onsemi.com 12 detailed description the ncp6914 is optimized to supply the different sub systems of battery powered portable applications. the ic can be supplied directly from the latest technology single cell batteries such as lithium?polymer as well as from triple alkaline cells. alternatively, the ic can be supplied from a pre?regulated supply rail in case of multi?cell or main powered applications. the output voltage range, current capabilities and performance of the switched mode dcdc converter are well suited to supply the different peripherals in the system as well as to supply processor cores. to reduce overall power consumption of the application, dynamic voltage scaling (dvs) is supported on the dcdc converter. for pwm operation, the converter runs on a local 3 mhz clock. a low power pfm mode is provided that ensures that even at low loads high efficiency can be obtained. all the switching components are integrated including the compensation networks and synchronous rectifier . only a small sized 1 h inductor and 10 f bypass capacitor are required for typical applications. the general purpose low dropout regulators can be used to supply the lower power rails in the application. to improve the overall application standby current, the bias current of these regulators are made very low. the regulators each have their own input supply pin to be able to connect them independently to either the system supply voltage or to the output of the dcdc converter in the application. the regulators are bypassed with a small size 2.2 f capacitor. all ic features can be controlled through the i 2 c interface. in addition to this bus, digital control pins including hardware enable (hwen), power good (pg), external synchronization (sync) and interrupt (intb) are provided. under voltage lockout the core does not operate for voltages below the under voltage lockout (uvlo) threshold and all internal circuitry, both analog and digital, is held in reset. ncp6914 functionality is guaranteed down to v uvlo when the battery is falling. a hysteresis is implemented to avoid erratic on / off behavior of the ic. due to its 200 mv hysteresis, re?start is guaranteed at 2.5 v when the battery is rising. thermal shutdown the thermal capabilities of the device can be exceeded due to the output power capabilities of the on chip step down converter and low drop out regulators. a thermal protection circuit is therefore implemented to prevent the part from being damaged. this protection circuit is only activated when the core is in active mode (at least one output channel is enabled). during thermal shutdown, all outputs of the ncp6914 are off. when the ncp6914 returns from thermal shutdown mode, it can re?start in two different configurations depending on rearm[1:0] bits. if rearm[1:0] = 00 then ncp6914 re?starts with default register values, otherwise it re?starts with register values set prior to thermal shutdown. in addition, a thermal warning is implemented which can inform the processor through an interrupt (if not masked) that ncp6914 is close to its thermal shutdown so that preventive measurement can be taken by software. active output discharge to prevent any disturbances on the power?up sequence, a quick active output discharge is done during the start?up sequence for all output channels. active output discharge can be independently enabled / disabled by the appropriate settings in the dis register (refer to the register definition section) when the ic is turned off through hwen pin or avin drops down below uvlo threshold, no shut down sequence is expected, all supplies are disabled and outputs discharged simultaneously enabling the hwen pin controls the device start up. if hwen is raised, this starts the power up sequencer. if hwen is made low, device enters in shutdown mode and all regulators are turned off. a built?in pull?down resistor disables the device if this pin is left unconnected. when hwen is high, the different power rails can be independently enabled / disabled by writing the appropriate bit in the enable register. power up/down sequence and hwen when enabling the part with the hwen pin, the part will start up in the configuration factory programmed in the registers. any order and output voltage setting can be factory programmed upon request. by default (ncp6914afcdt1g), the power up sequence is the following: table 5. default power up sequence for ncp6914afcdt1g delay (in ms) default assignment default v prog default mode and on/off 2 dcdc 1.20 v auto mode on 4 ldo1 1.80 v on 6 ldo2 1.80 v on 8 ldo3 2.80 v on 10 ldo4 2.80 v on
ncp6914 http://onsemi.com 13 figure 20. example of power up sequence t0 vout1 1.5 v vout4 2.8 v vout2 1.8 v vout3 2.8 v dcdc 1.2 v sequencer (2ms) * 36 ms (18 x tsequencer) t1 t2 t3 t4 t5 t6 t7 reset init time 160us dvs ramp time hwen t1 7 init time ~5 0 u s init time ~5 0 u s init time ~5 0 u s init time ~5 0 u s t start bias time ~7 0 u s *64 s, 128 s and 1 ms available upon request. i 2 c registers can be read and written while hwen pin is still low. by programming the appropriate registers (see registers description section), the power up sequence can be modified. reset to the factory default configuration can be achieved either by hardware reset (all power supplies removed) or by writing through the i 2 c in the reset register. table 6. power up sequencer delay (in ms) default assignment default v prog default mode and on/off NCP6914AFCAT1G 2 ldo1 1.20 v on 4 ldo2 1.80 v on 6 ldo3 2.80 v on 8 ldo4 2.80 v off 10 dcdc 2.80 v auto mode on ncp6914afcbt1g 2 ldo1 1.80 v on 2 ldo2 1.80 v on 4 ldo3 2.80 v on 4 ldo4 2.80 v on 6 dcdc 2.80 v auto mode on shutdown when shutting down the device, no shut down sequence is applied. all supplies are disabled and outputs are discharged simultaneously, and pg open drain is low whereas intb open drain is released. however, the power down sequence can be achieved by disabling dcdc/ldos via i2c before setting hwen pin to low. dynamic voltage scaling (dvs) the step down converter support dynamic voltage scaling (dvs). this means that the output voltage can be reprogrammed based upon the i 2 c commands to provide the different voltages required by the processor. the change between set points is managed in a smooth manner without disturbing the operation of the processor. when programming a higher voltage, the reference of the switcher and therefore the output is raised in equidistant steps per defined time period such that the dv/dt is controlled (by default 12.5 mv/1.33 s). when programming a lower voltage the output voltage will decrease accordingly. the dvs step is fixed and the speed is programmable.
ncp6914 http://onsemi.com 14 figure 21. dynamic voltage scaling effect timing diagram figure 22. dynamic voltage scaling example (ch1 = pg ? ch2 = v out ) programmability dcdc converter output voltage can be controlled by gox bit (time register) with vprogdcdc[7:0] / vdvsdcdc[7:0] registers, available output levels are listed in table vprogdcdc[7:0] and vdvsdcdc[7:0] register description. gox bit determines whether dcdc output voltage value is set in vprogdcdc[7:0] register or in vdvsdcdc[7:0] register . table 7. go bit description go bit description 0 output voltage is set to vprogdcdc 1 output voltage is set to vdvsdcdc the two dvs bits in the time register determine the ramp up time per each voltage step. table 8. dvs bits description dvs [1:0] bit description 00 1.33 s per step (default) 01 2.67 s per step 10 5.33us per step 11 10.67us per step there are two ways of i 2 c registers programming to switch the dcdc converters output voltages between different levels: 1. preset vprogdcdcx[7:0]/vdvsdcdcx[7:0] registers, and start dvs sequence by changing gox bit state. 2. gox bit remains unchanged, change output voltage value in either vprogdcdcx[7:0] or vdvsdcdcx[7:0] register. for example, the device needs to supply either 1.2 v or 0.9 v depending on working conditions. if using method 1, vprogdcdcx[7:0] and vdvsdcdcx[7:0] should be set as shown in t able 5. gox bit should be programmed to 1 to change dcdcx output voltage from 1.2 v to 0.9 v, and be programmed to 0 to move back from 0.9 v to 1.2 v. table 9. vprogdcdc / vdvsdcdc settings for vdcdc switching between 1.2 v and 0.9 v register name values target vdcdc (v) vprogdcdc 0$30 1.2 vdvsdcdc 0$18 0.9 external synchronization the ncp6914 allows synchronizing the dcdc converter to an external clock applied to the sync pin. during the power?up sequence (or power?up of the dcdc), the ic ignores any signal applied on the sync pin and the dcdc converter starts switching in normal operation on the internal 3 mhz clock. once the power?up sequence is terminated (or dcdc output is established), external synchronization is operational depending on the internal registers settings. if present, the signal frequency (f clock ) applied to the sync pin is divided by the syncratio[4:0] bits of the sync register to derive the internal f clockint . if f clockint = f clock / syncratio[4:0] = 3 mhz 15%, then the f clock is within operating frequency range. then, depending on the syncauto bit of sync register value, two cases can be considered: ? syncauto = 1: as soon as f clockint frequency is within the operating range, the dcdc converter clock will be f clockint . as soon as the f clockint frequency is out of the operating range, the dcdc converter clock will switch back to the internal 3 mhz clock ? syncauto = 0: as soon as f clockint frequency is within the operating range and syncen bit of sync register = 1, the dcdc converter clock will be f clockint . as soon as the f clockint frequency is out of the operating range or syncen bit of sync register = 0, the dcdc converter clock will switch back to the internal 3 mhz clock. if f clockint shifts
ncp6914 http://onsemi.com 15 out of the operating frequency range, the syncen bit is automatically reset to 0. sync interrupts clkok (external clock ok) and clksel (working clock selection) interrupt bits indicate about external clock validity and whether the dcdc converter works with the internal or external clock. refer to the interrupt description section for more detailed information about these two bits. programmability example for a particular application where the user wants the ncp6914 dcdc converter to be synchronized with a 19.2 mhz clock: ? sync[4..0] = 00110: the clock frequency applied to the sync pin will be divided by 6 by the controller. the result will be a typical 3.2 mhz. this frequency is within the 3.0 mhz 15% which is also within the sync operating range. ? syncauto = 1: the controller will continuously check the sync pin clock. syncen = 1: the function is enabled. eventually, the user should program 66h in the sync register so that the ic can operate with a 19.2 mhz clock on the sync pin. dcdc step down converter and ldo?s power good to indicate that the output of an output channel is established, a power good signal is available for each output channel. the power good signal is high when the channel is off and goes low when enabling the channel. once the output voltage reaches the expected output level, the power good signal becomes high again. when during operation the output gets below 90% of the expected level, the power good signal goes low which indicates a power failure. when the voltage rises again above 95% the power good signal is made high again. dcdc_en 160 us dcdc 95% 90% 4?9 us 4?9 us 5 us figure 23. dcdc channel internal power good signal pg figure 24. ldox channel internal power good signal ldox_en ldox pg 228? 265 us 5 us 228? 265 us 95% 90% power good assignment each channel generates an internal power good signal (either the dcdc or ldo?s). these internal power good signals can be individually assigned to the pg pin through the pgood1 register. the pg pin state is an and combination of assigned internal power good signals. by default only the power good signal of the dcdc converter is assigned. the pg pin is an open drain output. in addition, two other signals can be assigned to the pg pin: the internal reset signal register and the dvs signal through the pgood register. by assigning the internal reset signal, the pg pin is held low throughout the power up sequence and the reset period. by assigning the dvs signal of the dcdc converter, the pg pin is made low during the period the output voltage is being raised to the new setting as shown in figure 21. figure 25. pg operation in dvs sequence initial value final value dvs start dcdcx 95% of final value pg i 2 c power good delay a delay can be programmed between the moment the and result of the assigned internal power good signals becomes high and the moment the pg pin is released. the delay is set from 0 ms to 512 ms through the tor[2:0] bits in the time register. the default delay is 32 ms.
ncp6914 http://onsemi.com 16 figure 26. pg delay internal signal (result) of the assigned internal pg pg no delay delay programmed in tor[2:0] interrupt the interrupt controller continuously monitors internal interrupt sources, generating an interrupt signal when a system status change is detected (dual edge monitoring). the interrupt sources include: table 10. interrupt sources pg_dcdc power good of dcdc converter pg_ldo1 power good of ldo1 pg_ldo2 power good of ldo2 pg_ldo3 power good of ldo3 pg_ldo4 power good of ldo4 clkok external clock valid clksel working clock selection idcdc dcdc converter output over current ildo1 ldo1 output over current ildo2 ldo2 output over current ildo3 ldo3 output over current ildo4 ldo4 output over current uvlo uvlo state wnrg thermal warning tsd thermal shutdown individual bits generating interrupts will be set to 1 in the int_ack1/int_ack2 registers (i 2 c read only registers), indicating the interrupt source. int_ack1/int_ack2 registers are reset by an i 2 c read. int_sen1/int_sen2 registers (read only registers) are real time indicators of interrupt sources. all interrupt sources can be masked by registers int_msk1/int_msk2. masked sources will never generate an interrupt request on the intb pin. the intb pin is an open drain output. a non masked interrupt request will result in the intb pin driven low. when the host reads the int_ack1/int_ack2 registers, the intb pin is released to a high impedance state and the interrupt registers int_ack1/int_ack2 are cleared. the figure below shows how the dcdc converter power good produces an interrupt on the intb pin with int_sen1/int_msk1/int_ack1 and i 2 c read access (assuming no other interrupt happens during this read period). figure 27. interrupt timing chart example of pg_dcdc int_msk1 and int_msk2 registers are set to disable the intb feature by default during power?up. force reset and i2c interface disable the i 2 c interface can be disabled by the i2c_disable bit in the sync register. this saves current consumption which is especially important when all supply channels of the ncp6914 are disabled. to re?activate the i 2 c, the ic needs to be enabled through the hwen pin. the i 2 c registers can be reset by setting the forcerst bit in the reset register. it forces a restart of the device with its default settings. after start?up the rststatus bit defaults to 1 and can be cleared through the i 2 c. dcdc converter the converter can operate in two modes: pwm mode and pfm mode. in pwm mode the converter operates at a fixed frequency and adapts its duty cycle to regulate to the desired output voltage. the advantage of this mode is that the emi noise is predictable. however, at lower loadings the efficiency is degraded. in pfm mode some switching pulses are skipped to control the output voltage. this allows maintaining high efficiency even at low loadings. in addition, no high frequency clock is required which provides additional current savings. the switchover point between both modes is chosen depending on the supply conditions such that highest efficiency is obtained over the entire load range. the switch over between the pwm/pfm modes can occur automatically but the switcher can be set in forced pwm mode by i 2 c programming. a soft start is provided to limit inrush currents when enabling the converter. the soft start consists of ramping gradually the reference to the switcher. additional current limitation is provided by a peak current limiter that monitors and limits the current through the inductor. dcdc converter output voltage can be set by the i 2 c: modedcdc bit is used to program switcher mode control table 11. modedcdc bit description modedcdc dcdc mode control 0 mode is auto switching pfm / pwm 1 mode is pwm only
ncp6914 http://onsemi.com 17 i 2 c compatible interface ncp6914 can support a subset of i 2 c protocol, below are detailed introduction for i 2 c programming. i 2 c communication description on semiconductor communication protocol is a subset of the i 2 c protocol. figure 28. general protocol description start ic adress 1 1 read ack data 1 ack data n /ack stop start ack ic adress 0 0 write data 1 ack data n ack /ack stop from mcu to ncpxxxx from ncpxxxx to mcu read out from part write inside part if part does not acknolege, the /nack will be followed by a stop or sr. if part acknoleges, the ack can be followed by another data or stop or sr the first byte transmitted is the chip address (with lsb bit sets to 1 for a read operation, or sets to 0 for a write operation). then the following data will be: ? in case of a write operation, the register address (@reg) is followed by the data to be written in the chip. the writing process is incremental. so the first data will be written in @reg, the second one in @reg + 1 .... the data is optional. ? in case of read operation, the ncp6914 will output the data out from the last register that has been accessed by the last write operation. like the writing process, the reading process is an incremental process. read out from part the master will first make a ?pseudo write? transaction with no data to set the internal address register. then, a stop then start or a repeated start will initiate the read transaction from the register address and the initial write transaction has set: figure 29. read out from part stop ic adress 1 1 read ack start ic adress 0 0 write register adress ack start ack data 1 data n ack /ack stop stets internal register pointer register adress value register adress + (n ? 1) value n registers read from mcu to ncpxxxx from ncpxxxx to mcu
ncp6914 http://onsemi.com 18 the first write sequence will set the internal pointer on the register we want access to. then the read transaction will start at the address the write transaction has initiated. transaction with real write then read 1. with stop then start figure 30. write followed by read transaction reg + (n ? 1) value ack stop from mcu to ncpxxxx from ncpxxxx to mcu start ic adress 0 0 write ack register reg0 adress ack reg value ack sets internal register pointer write value in register reg0 write value in register reg0 + (n-1) n registers write ic adress 1 1 read start ack data 1 data k ack /ack stop regiister reg + (n ? 1) value register adress + (n ? 1) + (k ? 1) value k registers read write in part write operation will be achieved by only one transaction. after chip address, the mcu first data will be the internal register we want access to, then following data will be the data we want to write in reg, reg + 1, reg + 2, ...., reg +n. write n registers: figure 31. write in n registers reg + (n ? 1) value ack stop from mcu to ncpxxxx from ncpxxxx to mcu start ic adress 0 0 write ack register reg0 adress ack reg value ack sets internal register pointer write value in register reg0 write value in register reg0 + (n-1) n registers write i 2 c address ncp6914 has fixed i 2 c but different i 2 c address (0$10, 7 bit address, see below table a7~a1), ncp6914 supports 7?bit address only. table 12. ncp6914 i 2 c address i 2 c address hex a7 a6 a5 a4 a3 a2 a1 a0 default $20 / $21 0 0 1 0 0 0 0 x other addresses are available upon request.
ncp6914 http://onsemi.com 19 register map following register map describes i 2 c registers. registers can be: r read only register rc read then clear rw read and write register rwm read, write and can be modified by the ic reserved address is reserved and register is not physically designed spare address is reserved and register is physically designed address register name type default function $00 to 0$04 ? ? ? reserved. do not access to those registers $05 ? ? ? reserved for future use $06 to 0$0c ? ? ? reserved. do not access to those registers $0d to $1f ? ? ? reserved for future use $20 int_ack1 rc $00 interrupt 1 register (dual edge) $21 int_ack2 rc $00 interrupt 2 register (dual edge) $22 int_sen1 r $00 sense 1 register (real time status) $23 int_sen2 r $00 sense 2 register (real time status) $24 int_msk1 rw $ff mask 1 register to enable or disable interrupt sources $25 int_msk2 rw $ff mask 2 register to enable or disable interrupt sources $26 to $2f ? ? ? reserved for future use $30 reset rw $10 reset internal registers to default $31 pid r metal product identification (metal) $32 rid r metal revision identification (metal) $33 fid r fuse features identification (fuse) $34 enable rwm $3e enable and mode register $35 dis rw $1f active output discharge register $36 sync rwm $00 external synchronization setting register $37 pgood rw $41 power good pin assignment $38 time rw $00 timing definition $39 sequencer1 rw $08 sequencer register (dcdc and ldo1) $3a sequencer2 rw $1a sequencer register (ldo2 and ldo3) $3b sequencer3 rw $04 sequencer register (ldo4) $3c spare rw $00 spare register $3d to $3f ? ? ? reserved for future use $40 vprogdcdc rw $30 dcdc output voltage setting $41 vdvsdcdc rw $30 dcdc dvs output voltage setting $42 vprogldo1 rw $10 ldo1 output voltage setting $43 vprogldo2 rw $10 ldo2 output voltage setting $44 vprogldo3 rw $24 ldo3 output voltage setting $45 vprogldo4 rw $24 ldo4 output voltage setting $46 to $ff ? ? ? reserved. do not access to those registers details of the registers are in the following section.
ncp6914 http://onsemi.com 20 registers description table 13. int_ack1 register name: int_ack1 address: $20 type: rc default: $00 d7 d6 d5 d4 d3 d2 d1 d0 ack_clksel ack_clkok spare = 0 ack_pg_ldo4 ack_pg_ldo3 ack_pg_ldo2 ack_pg_ldo1 ack_pg_dcdc table 14. bit description of int_ack1 register bit bit description ack_pg_dcdc dcdc1 power good sense acknowledgement 0: cleared 1: dcdc power good event detected ack_pg_ldo1 ldo1 power good sense acknowledgement 0: cleared 1: ldo1 power good event detected ack_pg_ldo2 ldo2 power good sense acknowledgement 0: cleared 1: ldo2 power good event detected ack_pg_ldo3 ldo3 power good sense acknowledgement 0: cleared 1: ldo3 power good event detected ack_pg_ldo4 ldo4 power good sense acknowledgement 0: cleared 1: ldo4 power good event detected ack_clkok clkok sense acknowledgement 0: cleared 1: clkok event detected ack_clksel clksel sense acknowledgement 0: cleared 1: cklsel event detected table 15. int_ack2 register name: int_ack2 address: $21 type: rc default: $00 d7 d6 d5 d4 d3 d2 d1 d0 ack_tsd ack_wnrg ack_uvlo ack_ildo4 ack_ildo3 ack_ildo2 ack_ildo1 ack_idcdc table 16. bit description of int_ack2 register bit bit description ack_idcdc dcdc over current sense acknowledgement 0: cleared 1: dcdc1 over current event detected ack_ildo1 ldo1 over current sense acknowledgement 0: cleared 1: ldo1 over current event detected ack_ildo2 ldo2 over current sense acknowledgement 0: cleared 1: ldo2 over current event detected ack_ildo3 ldo3 over current sense acknowledgement 0: cleared 1: ldo3 over current event detected
ncp6914 http://onsemi.com 21 table 16. bit description of int_ack2 register bit bit description ack_ildo4 ldo4 over current sense acknowledgement 0: cleared 1: ldo4 over current event detected ack_uvlo under voltage sense acknowledgement 0: cleared 1: under voltage event detected ack_wnrg thermal warning sense acknowledgement 0: cleared 1: thermal warning event detected ack_tsd thermal shutdown sense acknowledgement 0: cleared 1: thermal shutdown event detected table 17. int_sen1 register name: int_sen1 address: $22 type: r default: $00 d7 d6 d5 d4 d3 d2 d1 d0 sen_clksel sen_clkok spare = 0 sen_pg_ldo4 sen_pg_ldo3 sen_pg_ldo2 sen_pg_ldo1 sen_pg_dcdc table 18. bit description of int_sen1 register bit bit description sen_pg_dcdc dcdc power good sense 0: dcdc output voltage below target 1: dcdc output voltage within nominal range sen_pg_ldo1 ldo1 power good sense 0: ldo1 output voltage below target 1: ldo1 output voltage within nominal range sen_pg_ldo2 ldo2 power good sense 0: ldo2 output voltage below target 1: ldo2 output voltage within nominal range sen _pg_ldo3 ldo3 power good sense 0: ldo3 output voltage below target 1: ldo3 output voltage within nominal range sen_pg_ldo4 ldo4 power good sense 0: ldo4 output voltage below target 1: ldo4 output voltage within nominal range sen_clkok external clock sense 0: divided clock is out of the 3.0 mhz range or off 1: divided clock is within the 3.0 mhz range sen_clksel operating clock sense 0: ncp6914 is operating on internal clock 1: ncp6914 operating on external clock table 19. int_sen2 register name: int_sen2 address: $23 type: r default: $00 d7 d6 d5 d4 d3 d2 d1 d0 sen_tsd sen_wnrg sen_uvlo sen_ildo4 sen_ildo3 sen_ildo2 sen_ildo1 sen_idcdc
ncp6914 http://onsemi.com 22 table 20. bit description of int_sen2 register bit bit description sen_idcdc dcdc over current sense 0: dcdc output current is below limit 1: dcdc output current is over limit sen_ildo1 ldo1 over current sense 0: ldo1 output current below limit 1: ldo1 output current over limit sen_ildo2 ldo2 over current sense 0: ldo2 output current below limit 1: ldo2 output current over limit sen_ildo3 ldo3 over current sense 0: ldo3 output current below limit 1: ldo3 output current over limit sen_ildo4 ldo4 over current sense 0: ldo4 output current below limit 1: ldo4 output current over limit sen_uvlo under voltage sense 0: input voltage higher than uvlo threshold 1: input voltage lower than uvlo threshold sen_wnrg thermal warning sense 0: junction temperature below thermal warning limit 1: junction temperature over thermal warning limit sen_tsd thermal shutdown sense 0: junction temperature below thermal shutdown limit 1: junction temperature over thermal shutdown limit table 21. int_msk1 register name: int_msk1 address: $24 type: rw default: $ff d7 d6 d5 d4 d3 d2 d1 d0 msk_clksel msk_clkok spare =1 msk_pg_ld o4 msk_pg_ldo3 msk_pg_ldo2 msk_pg_ldo1 msk_pg_dcdc table 22. bit description of int_msk1 register bit bit description msk_pg_dcdc dcdc power good interrupt source mask 0: interrupt is enabled 1: interrupt is masked msk_pg_ldo1 ldo1 power good interrupt source mask 0: interrupt is enabled 1: interrupt is masked msk_pg_ldo2 ldo2 power good interrupt source mask 0: interrupt is enabled 1: interrupt is masked msk_pg_ldo3 ldo3 power good interrupt source mask 0: interrupt is enabled 1: interrupt is masked msk_pg_ldo4 ldo4 power good interrupt source mask 0: interrupt is enabled 1: interrupt is masked
ncp6914 http://onsemi.com 23 table 22. bit description of int_msk1 register bit bit description msk_clkok external clock detection interrupt source mask 0: interrupt is enabled 1: interrupt is masked msk_clksel operating clock selection interrupt source mask 0: interrupt is enabled 1: interrupt is masked table 23. int_msk2 register name: int_msk2 address: $25 type: rw default: $ff d7 d6 d5 d4 d3 d2 d1 d0 msk_tsd msk_wnrg msk_uvlo msk_ildo4 msk_ildo3 msk_ildo2 msk_ildo1 msk_idcdc table 24. bit description of int_msk2 register bit bit description msk_idcdc dcdc over current interrupt mask 0: interrupt is enabled 1: interrupt is masked msk_ildo1 ldo1 over current interrupt mask 0: interrupt is enabled 1: interrupt is masked msk_ildo2 ldo2 over current interrupt mask 0: interrupt is enabled 1: interrupt is masked msk_ildo3 ldo3 over current interrupt mask 0: interrupt is enabled 1: interrupt is masked msk_ildo4 ldo4 over current interrupt mask 0: interrupt is enabled 1: interrupt is masked msk_uvlo uvlo interrupt mask 0: interrupt is enabled 1: interrupt is masked msk_wnrg thermal warning interrupt mask 0: interrupt is enabled 1: interrupt is masked msk_tsd thermal shutdown interrupt mask 0: interrupt is enabled 1: interrupt is masked table 25. reset register name: reset address: $30 type: rw default: $10 d7 d6 d5 d4 d3 d2 d1 d0 forcerst spare = 0 spare = 0 rststatus spare = 0 spare = 0 rearm[1:0]
ncp6914 http://onsemi.com 24 table 26. bit description of reset register bit bit description rearm[1:0] rearming of device after tsd 00 : re-arming active after tsd with reset of i 2 c registers: new power-up sequence is initiated with default i 2 c registers values (default) 01: re?arming active after tsd with no reset of i 2 c registers: new power?up sequence is initiated with i 2 c registers values 10: no re?arming after tsd 11: n / a rststatus reset indicator bit 0: must be written to 0 after register reset 1: default (loaded after registers reset) forcerst force reset bit 0: default 1: force reset of internal registers to default table 27. pid (product identification) register name: pid address: $31 type: r default: metal to $03 d7 d6 d5 d4 d3 d2 d1 d0 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 table 28. rid (revision identification) register name: rid address: $32 type: r default: metal to $00 d7 d6 d5 d4 d3 d2 d1 d0 rid7 rid6 rid5 rid4 rid3 rid2 rid1 rid0 table 29. fid (features identification) register name: fid address: $33 type: r default: fuse to $00 d7 d6 d5 d4 d3 d2 d1 d0 fid7 fid6 fid5 fid4 fid3 fid2 fid1 fid0 table 30. enable register name: enable address: $34 type: rwm default: fuse $3e d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 spare = 0 enldo4 enldo3 enldo2 enldo1 endcdc modedcdc table 31. bit description of enable register bit bit description modedcdc dcdc operating mode 0: auto switching pfm / pwm 1: forced pwm endcdc dcdc enabling 0: disabled 1: enabled
ncp6914 http://onsemi.com 25 table 31. bit description of enable register bit bit description enldo1 ldo1 enabling 0: disabled 1: enabled enldo2 ldo2 enabling 0: disabled 1: enabled enldo3 ldo3 enabling 0: disabled 1: enabled enldo4 ldo4 enabling 0: disabled 1: enabled table 32. dis register name: dis address: $35 type: rw default: $1f d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 spare = 0 spare = 0 disldo4 disldo3 disldo2 disldo1 disdcdc table 33. bit description of active output discharge register bit bit description disdcdc dcdc active output discharge 0: disabled 1: enabled disldo1 ldo1 active output discharge 0: disabled 1: enabled disldo2 ldo2 active output discharge 0: disabled 1: enabled disldo3 ldo3 active output discharge 0: disabled 1: enabled disldo4 ldo4 active output discharge 0: disabled 1: enabled table 34. sync register name: sync address: $36 type: rwm default: 0$00 d7 d6 d5 d4 d3 d2 d1 d0 i2c_disable syncen syncauto syncratio [4:0] table 35. bit description of sync register bit bit description syncratio[4:0] external clock divided ratio. refer to table 32 syncauto automatic external synchronization 0: automatic synchronization is disabled (controlled by syncen) 1: automatic synchronization enabled and external clock is continually verified
ncp6914 http://onsemi.com 26 table 35. bit description of sync register bit bit description syncen external synchronization enabling 0: disabled 1: enabled i2c_disable i 2 c interface enabling 0: enabled 1: disabled table 36. sync divider ratio vector bits description syncratio [4:0] sync ratio divider sync typical input frequency syncratio [4:0] sync ratio divider sync typical input frequency 00000 0 off 10000 16 00001 1 f clock = 3.0 mhz 10001 17 00010 2 10010 18 00011 3 10011 19 00100 4 f clock = 13 mhz 10100 20 00101 5 f clock = 15.36 mhz 10101 21 00110 6 f clock = 16.8 mhz f clock = 19.2 mhz 10110 22 00111 7 10111 23 01000 8 f clock = 24 mhz f clock = 26 mhz 11000 24 01001 9 11001 25 01010 10 11010 26 01011 11 f clock = 33.6 mhz 11011 27 01100 12 11100 28 01101 13 f clock = 38.4 mhz 11101 29 01110 14 11110 30 01111 15 11111 31 table 37. pgood register name: pgood address: $37 type: rw default: $41 d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 pgassign_rst pgassign_dvs pgassign_ldo4 pgassign_ldo3 pgassign_ldo2 pgassign_ldo1 pgassign_dcdc table 38. bit description of power good register bit bit description pgassign_dcdc dcdc power good assignment 0: not assigned 1: assigned to pg pin pgassign_ldo1 ldo1 power good assignment 0: not assigned 1: assigned to pg pin pgassign_ldo2 ldo2 power good assignment 0: not assigned 1: assigned to pg
ncp6914 http://onsemi.com 27 table 38. bit description of power good register bit bit description pgassign_ldo3 ldo3 power good assignment 0: not assigned 1: assigned to pg pin pgassign_ldo4 ldo4 power good assignment 0: not assigned 1: assigned to pg pin pgassign_dvs dcdc dvs assignment 0: not assigned 1: assigned to pg pin pgassign_rst internal reset signal assignment 0: not assigned 1: assigned to pg pin table 39. time register name: time address: $38 type: rw default: 0$00 d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 go spare = 0 dvs [1:0] tor[2:0] table 40. bit description of timing programmability register bit bit description tor[2:0] power good out of reset delay time (ms) 000: 0(default) 001: 8 010: 16 011: 32 100: 64 101: 128 110: 256 111: 512 dvs[1:0] dvs timing ( s) 00: 1.33 s (default) 01: 2.67 s 10: 5.33 s 11: 10.67 s go 0: dcdc output voltage set to vprogdcdc[7:0] 1: dcdc output voltage set to vdvsdcdc[7:0] table 41. sequencer1 register name: sequencer1 address: $39 type: rw default: $00 d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 spare = 0 spare = 0 spare = 0 spare = 0 dcdc_t[2:0] table 42. sequencer2 register name: sequencer2 address: $3a type: rw default: $11 d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 spare = 0 ldo2_t[2:0] ldo1_t[2:0]
ncp6914 http://onsemi.com 28 table 43. sequencer3 register name: sequencer3 address: $3b type: rw default: $23 d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 spare = 0 ldo4_t[2:0] ldo3_t[2:0] table 44. start?up delay ldox_t[2:0] / dcdc_t[2:0] start?up delay * 000 2 ms 001 4 ms 010 6 ms 011 8 ms 100 10 ms 101 12 ms 110 14 ms 111 16 ms *64 s, 128 s and 1 ms available upon request. table 45. vprogdcdc register name: vprogdcdc address: $40 type: rw default: $30 d7 d6 d5 d4 d3 d2 d1 d0 vprogdcdc[7:0] table 46. vdvsdcdc register name: vdvsdcdc address: $41 type: rw default: $30 d7 d6 d5 d4 d3 d2 d1 d0 vdvsdcdc[7:0] table 47. vprogdcdc[7:0] and vdvsdcdc[7:0] bits description bit[7:0] vout(v) bit [7:0] vout(v) bit [7:0] vout(v) bit [7:0] vout(v) $00 0.6000 $40 1.4000 $80 2.2000 $c0 3.0000 $01 0.6125 $41 1.4125 $81 2.2125 $c1 3.0125 $02 0.6250 $42 1.4250 $82 2.2250 $c2 3.0250 $03 0.6375 $43 1.4375 $83 2.2375 $c3 3.0375 $04 0.6500 $44 1.4500 $84 2.2500 $c4 3.0500 $05 0.6625 $45 1.4625 $85 2.2625 $c5 3.0625 $06 0.6750 $46 1.4750 $86 2.2750 $c6 3.0750 $07 0.6875 $47 1.4875 $87 2.2875 $c7 3.0875 $08 0.7000 $48 1.5000 $88 2.3000 $c8 3.1000 $09 0.7125 $49 1.5125 $89 2.3125 $c9 3.1125 $0a 0.7250 $4a 1.5250 $8a 2.3250 $ca 3.1250 $0b 0.7375 $4b 1.5375 $8b 2.3375 $cb 3.1375
ncp6914 http://onsemi.com 29 table 47. vprogdcdc[7:0] and vdvsdcdc[7:0] bits description bit[7:0] vout(v) bit [7:0] vout(v) bit [7:0] vout(v) bit [7:0] vout(v) $0c 0.7500 $4c 1.5500 $8c 2.3500 $cc 3.1500 $0d 0.7625 $4d 1.5625 $8d 2.3625 $cd 3.1625 $0e 0.7750 $4e 1.5750 $8e 2.3750 $ce 3.1750 $0f 0.7875 $4f 1.5875 $8f 2.3875 $cf 3.1875 $10 0.8000 $50 1.6000 $90 2.4000 $d0 3.2000 $11 0.8125 $51 1.6125 $91 2.4125 $d1 3.2125 $12 0.8250 $52 1.6250 $92 2.4250 $d2 3.2250 $13 0.8375 $53 1.6375 $93 2.4375 $d3 3.2375 $14 0.8500 $54 1.6500 $94 2.4500 $d4 3.2500 $15 0.8625 $55 1.6625 $95 2.4625 $d5 3.2625 $16 0.8750 $56 1.6750 $96 2.4750 $d6 3.2750 $17 0.8875 $57 1.6875 $97 2.4875 $d7 3.2875 $18 0.9000 $58 1.7000 $98 2.5000 $d8 3.3000 $19 0.9125 $59 1.7125 $99 2.5125 $d9 3.3000 $1a 0.9250 $5a 1.7250 $9a 2.5250 $da 3.3000 $1b 0.9375 $5b 1.7375 $9b 2.5375 $db 3.3000 $1c 0.9500 $5c 1.7500 $9c 2.5500 $dc 3.3000 $1d 0.9625 $5d 1.7625 $9d 2.5625 $dd 3.3000 $1e 0.9750 $5e 1.7750 $9e 2.5750 $de 3.3000 $1f 0.9875 $5f 1.7875 $9f 2.5875 $df 3.3000 $20 1.0000 $60 1.8000 $a0 2.6000 $e0 3.3000 $21 1.0125 $61 1.8125 $a1 2.6125 $e1 3.3000 $22 1.0250 $62 1.8250 $a2 2.6250 $e2 3.3000 $23 1.0375 $63 1.8375 $a3 2.6375 $e3 3.3000 $24 1.0500 $64 1.8500 $a4 2.6500 $e4 3.3000 $25 1.0625 $65 1.8625 $a5 2.6625 $e5 3.3000 $26 1.0750 $66 1.8750 $a6 2.6750 $e6 3.3000 $27 1.0875 $67 1.8875 $a7 2.6875 $e7 3.3000 $28 1.1000 $68 1.9000 $a8 2.7000 $e8 3.3000 $29 1.1125 $69 1.9125 $a9 2.7125 $e9 3.3000 $2a 1.1250 $6a 1.9250 $aa 2.7250 $ea 3.3000 $2b 1.1375 $6b 1.9375 $ab 2.7375 $eb 3.3000 $2c 1.1500 $6c 1.9500 $ac 2.7500 $ec 3.3000 $2d 1.1625 $6d 1.9625 $ad 2.7625 $ed 3.3000 $2e 1.1750 $6e 1.9750 $ae 2.7750 $ee 3.3000 $2f 1.1875 $6f 1.9875 $af 2.7875 $ef 3.3000 $30 1.2000 $70 2.0000 $b0 2.8000 $f0 3.3000 $31 1.2125 $71 2.0125 $b1 2.8125 $f1 3.3000 $32 1.2250 $72 2.0250 $b2 2.8250 $f2 3.3000 $33 1.2375 $73 2.0375 $b3 2.8375 $f3 3.3000
ncp6914 http://onsemi.com 30 table 47. vprogdcdc[7:0] and vdvsdcdc[7:0] bits description bit[7:0] vout(v) bit [7:0] vout(v) bit [7:0] vout(v) bit [7:0] vout(v) $34 1.2500 $74 2.0500 $b4 2.8500 $f4 3.3000 $35 1.2625 $75 2.0625 $b5 2.8625 $f5 3.3000 $36 1.2750 $76 2.0750 $b6 2.8750 $f6 3.3000 $37 1.2875 $77 2.0875 $b7 2.8875 $f7 3.3000 $38 1.3000 $78 2.1000 $b8 2.9000 $f8 3.3000 $39 1.3125 $79 2.1125 $b9 2.9125 $f9 3.3000 $3a 1.3250 $7a 2.1250 $ba 2.9250 $fa 3.3000 $3b 1.3375 $7b 2.1375 $bb 2.9375 $fb 3.3000 $3c 1.3500 $7c 2.1500 $bc 2.9500 $fc 3.3000 $3d 1.3625 $7d 2.1625 $bd 2.9625 $fd 3.3000 $3e 1.3750 $7e 2.1750 $be 2.9750 $fe 3.3000 $3f 1.3875 $7f 2.1875 $bf 2.9875 $ff 3.3000 table 48. vprogldo1 registers name: vprogldo1 address: $42 type: rw default: $10 d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 spare = 0 vprogldo1[5:0] table 49. vprogldo2 registers name: vprogldo2 address: $43 type: rw default: $10 d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 spare = 0 vprogldo2[5:0] table 50. vprogldo3 registers name: vprogldo3 address: $44 type: rw default: $24 d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 spare = 0 vprogldo3[5:0] table 51. vprogldo4 registers name: vprogldo4 address: $45 type: rw default: $24 d7 d6 d5 d4 d3 d2 d1 d0 spare = 0 spare = 0 vprogldo4[5:0]
ncp6914 http://onsemi.com 31 table 52. vprogldox[5:0] bits description vprogldox [5:0] vout (v) vprogldox [5:0] vout (v) vprogldox [5:0] vout (v) vprogldox [5:0] vout (v) $00 1.00 $10 1.80 $20 2.60 $30 3.30 $01 1.05 $11 1.85 $21 2.65 $31 3.30 $02 1.10 $12 1.90 $22 2.70 $32 3.30 $03 1.15 $13 1.95 $23 2.75 $33 3.30 $04 1.20 $14 2.00 $24 2.80 $34 3.30 $05 1.25 $15 2.05 $25 2.85 $35 3.30 $06 1.30 $16 2.10 $26 2.90 $36 3.30 $07 1.35 $17 2.15 $27 2.95 $37 3.30 $08 1.40 $18 2.20 $28 3.00 $38 3.30 $09 1.45 $19 2.25 $29 3.05 $39 3.30 $0a 1.50 $1a 2.30 $2a 3.10 $3a 3.30 $0b 1.55 $1b 2.35 $2b 3.15 $3b 3.30 $0c 1.60 $1c 2.40 $2c 3.20 $3c 3.30 $0d 1.65 $1d 2.45 $2d 3.25 $3d 3.30 $0e 1.70 $1e 2.50 $2e 3.30 $3e 3.30 $0f 1.75 $1f 2.55 $2f 3.30 $3f 3.30
ncp6914 http://onsemi.com 32 application information vout3 dcdc_vout l101 1uh sw1 vout1 fb1 vout3 vout4 vout2 vbat vout1 vout2 c111 2.2uf 6.3v c112 2.2uf 6.3v c113 2.2uf 6.3v vout4 c109 10uf 6.3v vin4 c110 2.2uf 6.3v pg vin3 vin12 vbat c108 100nf 6.3v hwen c107 10uf 6.3v scl sync avin c114 1uf 6.3v u102 ncp6914 pgnd1 e1 pvin1 d1 hwen c1 sync c3 pg b2 vout4 b1 vin4 a1 vin3 a2 vout3 a3 vbg a4 agnd b4 avin b3 vout2 e4 vin12 d4 vout1 c4 sda c2 scl d2 fb1 e3 intb d3 sw1 e2 pg, intb, scl and sca need pull?up resistor if not embedded in processor agnd and pgnd connected in one point intb sda figure 32. typical application schematic inductor selection ncp6914 dcdc converter typically uses 1 h inductor. use of different values can be considered to optimize operation in specific conditions. the inductor parameters directly related to device performances are saturation current, dc resistance and inductance value. the inductor ripple current ( i l ) decreases with higher inductance. v l v szie 7o 1 v o v in l f sw (eq. 1) i lmax i omax i l 2 (eq. 2) with: ? f sw = switching frequency (typical 3 mhz) ? l = inductor value ? i l = peak?t o?peak inductor ripple current ? i lmax = maximum inductor current to achieve better efficiency, ultra low dc resistance inductor should be selected. the saturation current of the inductor should be higher than the i lmax calculated with the above equations. table 53. inductor l = 1.0 h manufacturer part number case size height typ. (mm) l ( h) murata lqm2hpn1r0mg0 2.5 x 2.0 1.0 1.0 murata lqh33pn1r0nj0 3.0 x 3.0 1.2 1.0 murata lqh44pn1r0nj0 4.0 x 4.0 1.8 1.0 tdk vls201612et?1r0 2.0 x 1.6 1.2 1.0
ncp6914 http://onsemi.com 33 table 54. inductor l = 2.2 h manufacturer part number case size height typ. (mm) l ( h) murata lqm2hpn2r2mg0 2.5 x 2.0 1.0 2.2 murata lqh44pn2r2mp0 4.0 x 4.0 1.8 2.2 tdk vls201612et?2r2 2.0 x 1.6 1.2 2.2 output capacitor selection for dcdc converter selecting the proper output capacitor is based on the desired output ripple voltage. ceramic capacitors with low esr values will have the lowest output ripple voltage and are strongly recommended. the output capacitor requires either an x7r or x5r dielectric. the output ripple voltage in pwm mode is given by: v o v o 1 v o v in l f sw 1 2 c o f esr (eq. 3) table 55. recommended output capacitor for dcdc converter manufac- turer part number case size height typ. (mm) c ( f) murata grm188r60j106me47 0603 0.8 10 murata grm219r60j106ke19 0805 1.25 10 murata grm21br60j226me39 0805 1.25 22 tdk c1608x5r0c106k/m 0603 0.8 10 tdk c2012x5r0c106k/m 0805 1.25 10 tdk c2012x5r0c226k/m 0805 1.25 22 input capacitor selection for dcdc converter in pwm operating mode, the input current is pulsating with large switching noise. using an input bypass capacitor can reduce the peak current transients drawn from the input supply source, thereby reducing switching noise significantly. the capacitance needed for the input bypass capacitor depends on the source impedance of the input supply. the maximum rms current occurs at 50% duty cycle with maximum output current, which is 1/2 of maximum output current. a low profile ceramic capacitor of 4.7 f should be used for most of the cases. for effective bypass results, the input capacitor should be placed as close as possible to the vin pin. table 56. recommended input capacitor for dcdc converter manufac- turer part number case size height typ. (mm) c ( f) murata grm188r60j475ke 0603 0.8 4.7 murata grm188r60j106me 0603 0.8 10 tdk c1608x5r0c475k/m 0603 0.8 4.7 tdk c1608x5r0c106k/m 0603 0.8 10 output capacitor selection for ldos for stability reason, a typical 2.2 f output capacitor is suitable for ldos. the output capacitor should be placed as close as possible to the ncp6914 output pin. input capacitor selection for ldos ncp6914 ldos do not require specific input capacitor. however, an input typical 1uf ceramic capacitor placed close to ncp6914 is helpful for load transient. input of ldo can be connected to main power supply. however, for optimum efficiency and lower ncp6914 thermal dissipation, lowest voltage available in the system is preferred. input voltage of ldo, should always be higher than v out + v drop (v drop , being the dropout voltage at maximum current). capacitor dc bias characteristics real capacitance of ceramic capacitor changes versus dc voltage. special care should be taken to dc bias effect in order to make sure that the real capacitor value is always higher than the minimum allowable capacitor value specified.
ncp6914 http://onsemi.com 34 pcb layout recommendation the high speed operation of the ncp6914 demands careful attention to board layout and component placement. to prevent electromagnetic interference (emi) problems and reduce voltage ripple of the device any high current copper trace which see high frequency switching should be optimized. therefore, use short and wide traces for power current paths and for power ground tracks. both the inductor and input/output capacitor of dcdc converter are in the high frequency switching path where current flow may be discontinuous. these components should be placed as close as possible to reduce parasitic inductance connection. also it is important to minimize the area of the switching nodes and used the ground plane under them to minimize cross?talk to sensitive signals and ic. it?s suggested to keep as c omplete ground plane under ncp6914 as possible. pgnd and agnd pin connection must be connected to the ground plane. care should be taken to avoid noise interference between pgnd and agnd. finally it is always good practice to keep the sensitive tracks such as feedback connection (fb1) away from switching signal connections (sw1) by laying the tracks on the other side or inner layer of pcb. figure 33. recommended pcb layout
ncp6914 http://onsemi.com 35 thermal considerations careful attention must be paid to the internal power dissipation of the ncp6914. the power dissipation is a function of efficiency and output power. hence, increasing the output power requires better components selection. care should be taken of dropout voltage of ldos, the larger it is, the higher dissipation it will bring to ncp6914. keep large copper plane under and close to ncp6914 is helpful for thermal dissipation too. ordering information device marking package shipping ? ncp6914afcdt1g (default)* 6914ad wlcsp20 ? 1.77 x 2.06 mm (pb?free) 3000 / tape & reel NCP6914AFCAT1G* 6914aa wlcsp20 ? 1.77 x 2.06 mm (pb?free) 3000 / tape & reel ncp6914afcbt1g* 6914ab wlcsp20 ? 1.77 x 2.06 mm (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *this is flip chip package without die coating demo board available: the ncp6914gevb/d evaluation board configures the device in typical application to supply constant voltage.
ncp6914 http://onsemi.com 36 package dimensions wlcsp20, 1.77x2.06 case 567cv issue a seating plane 0.10 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min max ??? millimeters a1 d 1.77 bsc e b 0.24 0.29 e 0.40 bsc 0.60 d e a b pin a1 reference e a 0.05 b c 0.03 c 0.05 c 20x b 4 c b a 0.10 c a a1 a2 c 0.17 0.23 2.06 bsc 0.25 20x dimensions: millimeters *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.40 0.40 0.10 c 2x top view side view bottom view note 3 e a2 recommended package outline 123 pitch d e pitch a1 0.33 0.39 e/2 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp6914/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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